FPGA based multi-core architectures for deep learning networks


Hua Chen

Date of Award


Degree Name

M.S. in Electrical Engineering


Department of Electrical and Computer Engineering


Advisor: Tarek Taha


Deep learning a large scalable network architecture based on neural network. It is currently an extremely active research area in machine learning and pattern recognition society. They have diverse uses including pattern recognition, signal processing, image processing, image compression, classification of remote sensing data, and big data processing. Interest in specialized architectures for accelerating deep learning networks has increased significantly because of their ability to reduce power, increase performance, and allow fault tolerant computing. Specialized neuromorphic architectures could provide high performance at extreme low powers for these applications. This thesis concentrates on the implementation of multi-core neuromorphic network architecture on FPGA. Hardware prototyping of wormhole router unit is developed to control transmission of data packets running through between cores. Router units connect multiple cores into a large scalable network. This network is programmed on a Stratix IV FPGA board. Additionally, a memory initialization system is design inside the core to realize external network configuration. In this approaching, different applications could be mapped on the network without repeating FPGA compilation. One application called Image Edge Detection is mapped on the network. Finally this network outputs the desired image and demonstrate 3.4x run time efficiency and 3.6x energy-delay efficiency by FPGA implementation.


Neural networks (Computer science) Design and construction, Field programmable gate arrays, Electrical Engineering, Deep learning network, FPGA, neuromorphic processor, Wormhole router

Rights Statement

Copyright 2015, author