Data transfer system for host computer and FPGA communication
Date of Award
M.S. in Electrical Engineering
Department of Electrical and Computer Engineering
Advisor: Eric John Balster
This thesis describes a communication system to allow for the transmission of data between a host computer and a DE2-115 FPGA board over an Ethernet connection. This is achieved by using a socket between the host computer and a NIOS II embedded processor that accepts the data from the host computer and transfers it to the FPGA fabric. The host computer uses a C++ program to open a file and send the data over the socket to the NIOS II processor. The NIOS II acts as memory controller for the Synchronous Dynamic Random Access Memory (SDRAM) on the board with separate input and output data sections for the Hardware Description Language (HDL) processing module. A HDL module then processes the data and sends it back to the NIOS II to be returned to the host computer over the socket. The data transfer system is tested with three basic image processing functions performed on three sample images to verify its functionality. This data transfer system allows for easier testing of digital designs on the DE2-115 board by providing test data to the digital design in an efficient manner.
Data transmission systems, Field programmable gate arrays, Electrical Engineering, Data Transfer, FPGA Board, NIOS II Processor, Sockets, Ethernet, TCP IP
Copyright 2015, author
Barnard, Michael T., "Data transfer system for host computer and FPGA communication" (2015). Graduate Theses and Dissertations. 1090.