Title

Netlist security algorithm acceleration using OpenCL on FPGAs

Date of Award

2017

Degree Name

M.S. in Computer Engineering

Department

Department of Electrical and Computer Engineering

Advisor/Chair

Advisor: Eric John Balster

Abstract

Integrated circuits continue to grow in number of transistors and design complexity. Production of many of these components are also outsourced to facilities in a number of countries. Therefore, there is a need to ensure all parts within a system are reliable and free from modification. Verification tools must be able to assess circuits down to a gate level but also be scalable to assess complex designs. In response to this problem, an accelerated version of the Integrated Circuit Verification Software is proposed to determine if a manufacturer design is the same as a known, reference design by comparing the two netlists. Optimizations are made to the Python code, and an FPGA hardware accelerated version of the code is created using OpenCL. Results of the OpenCL implementation show an 18x to 24x speedup across various netlists. Additionally, a netlist previously too large for verification tools to run is able to be tested by the OpenCL algorithm.

Keywords

Computer software Verification, Electronic circuits Evaluation, Computer algorithms, Computer Engineering, Electrical Engineering, OpenCL, netlist, FPGA, DFF, verification, security, Python, gate, ctypes, fan in, fan out, flatten, hash, integrated circuit, acceleration, speedup

Rights Statement

Copyright 2017, author

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