FPGA implementation of the JPEG2000 MQ decoder
Date of Award
2010
Degree Name
M.S. in Electrical Engineering
Department
Department of Electrical and Computer Engineering
Advisor/Chair
Advisor: Eric J. Balster
Abstract
As digital imaging techniques continue to advance, new image compression standards are needed to keep the transmission time and storage space low for increasing image sizes. The Joint Photographic Expert Group (JPEG) fulfilled this need with the ratification of the JPEG2000 standard in December of 2000. JPEG2000 adds many features to image compression technology but also increases the computational complexity of traditional decoders. To mitigate the added computational complexity, the committee developed the JPEG2000 algorithm to process parts in parallel, increasing the benefits of implementing the algorithm in application specific integrated circuits (ASICs) or field programmable gate arrays (FPGAs). A flexible FPGA implementation of the MQ Decoder, the core component of the JPEG2000 decoding algorithm, is presented in this paper that successfully increases the throughput beyond previous designs.
Keywords
JPEG (Image coding standard), Field programmable gate arrays, Image compression Standards
Rights Statement
Copyright © 2010, author
Recommended Citation
Lucking, David Joseph, "FPGA implementation of the JPEG2000 MQ decoder" (2010). Graduate Theses and Dissertations. 256.
https://ecommons.udayton.edu/graduate_theses/256
