Document Type

Article

Publication Date

8-2017

Publication Source

Microelectronics Journal

Abstract

Memristor crossbar arrays carry out multiply-add operations in parallel in the analog domain, and so can enable neuromorphic systems with high throughput at low energy and area consumption. On-chip training of these systems have the significant advantage of being able to get around device variability and faults. This paper presents on-chip training circuits for multi-layer neural networks implemented using a single crossbar per layer and two memristors per synapse. Using two memristors per synapse provides double the synaptic weight precision when compared to a design that uses only one memristor per synapse. Proposed on-chip training system utilizes the back propagation (BP) algorithm for synaptic weight update. Due to the use of two memristors per synapse, we utilize a novel technique for error back propagation. We evaluated the training of the system with some nonlinearly separable datasets through detailed SPICE simulations which take crossbar wire resistance and sneak-paths into consideration. Our results show that in the proposed design, the crossbars consume about 9x less power than single memristor per synapse design.

Inclusive pages

31-40

ISBN/ISSN

0026-2692

Document Version

Published Version

Comments

This open-access article is provided for download in compliance with the publisher’s policy on self-archiving. To view the version of record, use the DOI: https://doi.org/10.1016/j.mejo.2017.05.005

Publisher

Elsevier Sci LTD

Volume

66

Peer Reviewed

yes

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