OpenCL acceleration of the KLT feature tracker on an FPGA
Date of Award
2017
Degree Name
M.S. in Computer Engineering
Department
Department of Electrical and Computer Engineering
Advisor/Chair
Advisor: Eric John Balster
Abstract
The Kanade-Lucas-Tomasi (KLT) algorithm is a well known feature tracker that has been implemented on both CPUs and GPUs. When tracking large numbers of features in high definition video, the KLT feature tracker does not execute in close to real-time. In order to remedy this, the KLT feature tracker has been implemented on a GPU. However, the GPU requires high energy costs. The FPGA is a low power device that can be used to accelerate programs. This research focuses on accelerating the KLT feature tracker on an Altera Arria 10 FPGA using the parallel, cross-platform OpenCL framework. The purpose is to provide a low power solution that also shows accelerated performance. As a result, the Arria 10 FPGA is able to obtain over a 50% decrease in run-time compared to the CPU. The FPGA design was also able to achieve over 30% power efficiency over the GPU implementation and 98% power efficiency over the CPU implementation.
Keywords
Field programmable gate arrays, Image reconstruction, Computer capacity, Computer Engineering, KLT, FPGA, OpenCL
Rights Statement
Copyright © 2017, author
Recommended Citation
DeMange, Ashley, "OpenCL acceleration of the KLT feature tracker on an FPGA" (2017). Graduate Theses and Dissertations. 1277.
https://ecommons.udayton.edu/graduate_theses/1277
