XILINX FPGA design for implementation of IEEE format 32-bit floating-point arithmematic [i.e. arithmetic]

Author

Yuan Zhang, University of Dayton

Date of Award

1998

Degree Name

M.S. in Electrical Engineering

Department

Department of Electrical and Computer Engineering

Keywords

Computer programming, Gate array circuits, Field programmable gate arrays, Floating-point arithmetic, VHDL (Computer hardware description language)

Rights Statement

Copyright © 1998, author

Recommended Citation

Zhang, Yuan, "XILINX FPGA design for implementation of IEEE format 32-bit floating-point arithmematic [i.e. arithmetic]" (1998). Graduate Theses and Dissertations. 6563.
https://ecommons.udayton.edu/graduate_theses/6563