A High-Resolution Multi-Channel Time to Digital Converter Using a Novel Wave Union Method
Date of Award
12-12-2024
Degree Name
Ph.D. in Electrical and Computer Engineering
Department
Department of Electrical and Computer Engineering
Advisor/Chair
Vamsy P. Chodavarapu
Abstract
Time-to-digital converters (TDCs) are frequently employed in Time-of-Flight (ToF) measurement applications due to their ability to compute the elapsed time between two pulses in the digital format. Field-Programmable Gate Arrays (FPGAs) can host efficient TDC architectures that could achieve picosecond-time resolution. FPGA-based TDCs, thus could support state-of-the-art applications in the physics, automotive, and medical imaging domains. Despite their exceptional performance, current TDCs often face trade-offs between precision, size, weight, power, and cost. Furthermore, existing architectures are prone to non-linearities that impact their resolution. This thesis addresses some of these problems by presenting a new TDC architecture design, especially for applications needing high-precision time interval measurements while preserving efficient size, weight, power, and cost (SWaP-C) specifications. This work primarily contributes to the sub-interpolation approach, which provides an efficient way to enhance the resolution of FPGA-based TDCs such as the Wave Union (WU) techniques. We developed a Tapped Delay Line (TDL) based TDC architecture using Wave Union type A (WU-A) paradigm. The proposed architecture is suitable for applications requiring high-precision time interval measurements with efficient SWaP-C criteria. Furthermore, we enhanced WU-A to mitigate the impact of bubble errors. The proposed TDC design is implemented on a low-cost Xilinx FPGA Artix-7 board to attain remarkable SWaP-C efficiency. The results show that the proposed architecture has reduced the computational overhead considerably by using a single multiplexer in a novel way to produce the wave union pulse train when the start signal arrives. In addition to architectural developments, the work in this thesis provides an autocalibration method that handles defects in Differential Non-Linearity (DNL) and Integral Non-Linearity (INL) to improve measuring resolution. Root Mean Square resolution of around 1.81 Ps and average time precision of less than 3 Ps is achieved by combining new TDC architecture and auto-calibration algorithm on an FPGA implementation. Moreover, the suggested TDC design combines designs to lower dead time, lower time jitter, keep a low power consumption of 1.935 W, and limit DNL to < ±1.9 LSB (1LSB = 0.673 Ps). It highlights the potential of the proposed architecture to revolutionize various fields that require a precise timing measurement of digital signals.
Keywords
time to digital converter (TDC), field programmable gate array (FPGA), wave union (WU), tapped delay line (TDL).
Rights Statement
Copyright © 2024, author.
Recommended Citation
Alshahry, Saleh, "A High-Resolution Multi-Channel Time to Digital Converter Using a Novel Wave Union Method" (2024). Graduate Theses and Dissertations. 7461.
https://ecommons.udayton.edu/graduate_theses/7461
