Reducing FIR filter costs: a review of approaches as applied to massive fir filter arrays
Date of Award
2014
Degree Name
M.S. in Electrical Engineering
Department
Department of Electrical and Computer Engineering
Advisor/Chair
Advisor: John G. Weber
Abstract
Digital signal processing designs are getting larger. At the same time modern applications are demanding smaller and smaller form factors. This project is a design with a specific problem. The design is a massive Multiple-Input-Multiple-Output FIR filter array. Currently the design is supported using multiple FPGAs. The problem is getting the entire FIR filter array to fit into a single FPGA. To reduce the size of the array, this paper looked at methods of reducing the size of FIR filters. Multiple approaches were reviewed: linear-phase filters, sparse filters, multichannel filters, multirate filters and filter banks. Each approach was implemented in VHDL for simulation and synthesis results. Based on the results, each approach can be analyzed for costs and tradeoffs. Based on the analysis, two of the approaches show the most promise for massive FIR filter arrays. Those two approaches are the multichannel and the filter bank approaches. These two approaches have their limitations. However within those limitations either approach can support large FIR filter arrays within a single FPGA.
Keywords
Signal processing Digital techniques, Field programmable gate arrays Computer-aided design, Field programmable gate arrays Design and construction, Digital filters (Mathematics), Computer Engineering, Electrical Engineering, DSP, digital signal processing, FIR filter, cost, efficiency, FPGA, linear phase, sparse, multichannel, multirate, filter bank
Rights Statement
Copyright © 2014, author
Recommended Citation
Dallmeyer, Matthew John, "Reducing FIR filter costs: a review of approaches as applied to massive fir filter arrays" (2014). Graduate Theses and Dissertations. 764.
https://ecommons.udayton.edu/graduate_theses/764
